SRAM
UT8ER512K32 16Mb Asynchronous Monolithic SRAM
- Density and organization
- 16 Mb; 512K × 32
- Read/write access
- 20 ns read; 10 ns write
- Nominal supplies
- I/O: 3.3 V; core: 1.8 V
Specifications
| Part Number | UT8ER512K32 |
|---|---|
| Flight Grade | QML-Q, QML-V |
| LET (MeV-cm^2/mg) | ≤111 |
| TID krad(Si) | 100 |
| Access Time | 20ns |
| Configuration | 512K x 32 |
| Density | 16Mb |
| Supply Voltage | +3.3V |
| Package | 68-Lead FP |
Technical specifications
| Specification | Value | Notes |
|---|---|---|
| Density and organization | 16 Mb; 512K × 32 | |
| Read/write access | 20 ns read; 10 ns write | |
| Nominal supplies | I/O: 3.3 V; core: 1.8 V | |
| Package | 68-lead ceramic quad flatpack | |
| SMD operating range | −55°C to +125°C | |
| SMD radiation assurance | 100 krad(Si) | RHA option; generic HiRel and prototype flows do not guarantee radiation performance. |
| Modeled heavy-ion error rate | 8.1 × 10⁻¹⁶ errors/bit-day | 90% worst-case GEO particle environment, 100 mil aluminum shielding and default EDAC scrub rate. This is not a universal mission error rate. |
Values are subject to the conditions and ordering options in the referenced product documentation.
Product overview
The UT8ER512K32 is a 16 Mb monolithic CMOS SRAM organized as 512K × 32, with embedded error detection and correction. It offers 20 ns read and 10 ns write access and uses separate 3.3 V I/O and 1.8 V core supplies. Programmable master and slave scrub modes let the system balance error correction against memory availability. Single-bit errors are corrected on read output, while periodic scrubbing rewrites corrected data into the memory array. Active-low and active-high enables, output enable and three-state drivers support bus control. The device is supplied in a 68-lead ceramic quad flatpack, with SMD-defined quality and radiation-assurance options.
Documentation
Technical documents and resources
For product questions or additional technical information, contact Frontgrade https://www.frontgrade.com/contact-us-form.
Datasheet
Application Notes
Memory Power Calculator
IBIS Models
More about this product
Product features
- Embedded EDAC with programmable scrub timing
- Master and slave device options
- Asynchronous SRAM-compatible interface
- Deselected power-down mode
Read correction and array scrubbing
Read cycles correct single-bit errors on the output bus without rewriting the core array. Periodic scrub cycles perform the array correction, limiting accumulation of memory upsets.
Programmable scrub scheduling
A master device scrubs at the programmed period. A slave device scrubs when SCRUB is asserted, allowing system-controlled scheduling.
Applications
- Microprocessor memory
- Microcontroller memory
- FPGA memory
Discuss your application
Contact Frontgrade to discuss UT8ER512K32 16Mb Asynchronous Monolithic SRAM and the requirements of your application.