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UT8ER512K32M SRAM Memory

Frontgrade memory products are for your applications requiring the highest reliability in extreme environments.

The UT8ER512K32 is a 16Mb, 512K x 32, high performance CMOS static RAM with EDAC. This device has a power-down feature that reduces power consumption by more than 90% when deselected. Ideal for fault tolerant designs in harsh space environments.

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Overview
  • Features:
  • 16Mb, 512K x 32
  • EDAC
  • 20ns Read, 10ns Write Maximum Access Time
  • Compatible with Industry Standard 512K x 32 SRAMs 
  • TTL Compatible Inputs and Output Levels
  • Three-State Bidirectional Data Bus
  • +3.3V I/O Voltage, +1.8V Core Voltage
  • Applications:
  • Ideal for fault tolerant designs in harsh space environments
  • Operational Environment:
  • Temperature Range: -55°C to +125°C
  • Total Ionizing Dose: <100 krad (Si)
  • SEL Immune: ≤111 MeV-cm2/mg
  • SEU Rate: <8.1 x E-16 errors/bit-day
  • Physical:
  • 68-Pin Ceramic Quad Flatpack
  • Power:
  • 5W (maximum package power dissipation)
  • Flight Grade:
  • QML-Q, QML-V
  • Export Control Classification Number (ECCN):
  • 9A515.e.1
  • SMD Number:
  • 5962-06261

ADDITIONAL SPECIFICATIONS

Defense Logistics Agency

Key Tech Specs

Datasheet

Datasheet-UT8ER512K32.pdf

 

Application Notes

App-Note-SRAM-ReadOperations.pdf

App-Note-UT8ER512K32-DesignHandbook.pdf

App-Note-SRAM-CE

 

Memory Power Calculator

Spreadsheet_MemoryPowerCalculator_final ver2016.1.xlsx 

 

IBIS Model

ut8er512k32m.ibs

ut8er512k32s.ibs

 

ADEPT Notifications

SPO-2018-PIN-0003
SMD/Datasheet corrections to include missing AC timing specs and edir VDD and VIO absolute max rating

SPO-2012-PA-0001
Corrected and New AC parameters for EDAC register access

SPO-2012-PCN-0007
SEE Limits corrections

SPO-2015-AL-0001
An internal review determined Total Ionizing Dose (TID) testing bias circuit was limiting current when performing radiation testing to 100 krad(Si) per MIL-STD-883, M1019, Condition A. As a result of this finding, samples from previously delivered wafer

SPO-2015-PIN-0003
Product Information Notice is to inform the industry about the CAES SRAMs low power read architecture

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