SRAM
UT8ER2M32 64Mb SRAM Module
- Density and organization
- 64 Mb; 2M × 32
- SEL characterization
- ≤110 MeV·cm²/mg
- Type
- SRAM
Specifications
| Part Number | UT8ER2M32 |
|---|---|
| Flight Grade | QML-Q, QML-V |
| LET (MeV·cm²/mg) | ≤110 |
| TID krad(Si) | 100 |
| Access Time | 22ns |
| Configuration | 2M x 32 |
| Density | 64Mb |
| Supply Voltage | +2.5V |
| Package | 132-Lead FP |
Technical specifications
| Specification | Value | Notes |
|---|---|---|
| Density and organization | 64 Mb; 2M × 32 | |
| Read/write access | 22 ns read; 10 ns write | Use this density-specific option; the family feature heading does not make all densities 20 ns. |
| I/O and core supplies | I/O: 2.3–3.6 V; core: 1.7–2.0 V | |
| Package | 132-lead side-brazed dual-cavity ceramic quad flatpack | |
| HiRel operating range | −55°C to +105°C | Prototype flow is 25°C only. |
| SMD radiation assurance | 100 krad(Si) | SMD R option. Generic HiRel and prototype flows do not test or guarantee radiation. |
| SEL characterization | ≤110 MeV·cm²/mg |
Values are subject to the conditions and ordering options in the referenced product documentation.
Product overview
The UT8ER2M32 is a 64 Mb CMOS static RAM multichip module organized as 2M × 32. It combines four SRAM die in a 132-lead ceramic quad flatpack and provides 22 ns read access with 10 ns write access. Active-low chip enables, output enable and three-state drivers support memory expansion and bus control. Embedded error detection and correction supports master or slave scrubbing, with programmable scrub timing to balance data protection and memory availability. A deselected power-down mode reduces consumption while preserving stored data. Core and I/O supplies are separate, and the selected SMD ordering configuration defines radiation assurance, temperature range and quality level.
Documentation
Technical documents and resources
For product questions or additional technical information, contact Frontgrade https://www.frontgrade.com/contact-us-form.
Datasheet
Application Notes
Memory Power Calculator
IBIS Models
More about this product
Product features
- Asynchronous SRAM interface
- Separate I/O and core supplies
- Three-state bidirectional data bus
- Deselected power-down mode
- Programmable EDAC scrubbing
- Master and slave options
Programmable memory scrubbing
Embedded EDAC corrects single-bit errors presented on the output bus during reads. Core memory is rewritten only during scrub cycles, so periodic scrubbing is required to prevent accumulation of errors.
Master and slave options
Master devices initiate scrub cycles at a programmed interval. Slave devices perform a scrub cycle when requested through the SCRUB input.
Applications
- Microprocessor memory
- Microcontroller memory
- FPGA memory
Discuss your application
Contact Frontgrade to discuss UT8ER2M32 64Mb SRAM Module and the requirements of your application.