The UT8R2M39 is an 80Mb, radiation hardened by design, high performance CMOS static RAM multichip module (MCM) that is functionally compatible with traditional 2Mx39 SRAM devices.

The device has a power-down feature that reduces power consumption by more than 90% when deselected, offered in a single package solution, and has superior SEU performance. Ideal for code execution in high performance microprocessors, microcontrollers and FPGAs.

Overview
  • Features:
  • 80Mb, 2M x 39
  • Asynchronous Interface
  • External EDAC Support
  • 20ns Read, 10ns Write Access Time
  • Functionally compatible with traditional 2M x 39 SRAM devices 
  • CMOS compatible input and output levels
  • Three-state bidirectional data bus
  • Supply Voltage: +2.3V to +3.6V (Supply), +1.7V to +2.0V (Core)
  • Applications:
  • Microprocessors, microcontrollers, FPGAs
  • Operational Environment:
  • Temperature Range: -55°C to +105°C
  • Total Ionizing Dose: <100 krad (Si)
  • SEL Immune: ≤110 MeV-cm2/mg
  • SEU Rate: <7.3 x E-7 errors/bit-day
  • Physical:
  • 132-Pin side-brazed Dual Cavity Ceramic Quad Flatpack
  • Power:
  • 2W
  • Flight Grade:
  • QML-Q, QML-Q+, QML-V 
  • Export Control Classification Number (ECCN):
  • 9A515.e.1
  • SMD Number:
  • 5962-10206

ADDITIONAL SPECIFICATIONS

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Key Tech Specs

Datasheet

Datasheet-UT8RxM39.pdf

 

Application Notes

App-Note-SRAM-ReadOperations.pdf

App-Note-SRAM-CE

 

Memory Power Calculator

Spreadsheet_MemoryPowerCalculator_final ver2016.1.xlsx 

 

IBIS Model

UT8R2M39.zip

 

ADEPT Notifications

SPO-2020-PA-0006D
Group D Seam Seal failure of microcircuit, memory, digital, CMOS, radiation-hardened, dual-voltage SRAM, Multichip Module

SPO-2015-AL-0001
An internal review determined Total Ionizing Dose (TID) testing bias circuit was limiting current when performing radiation testing to 100 krad(Si) per MIL-STD-883, M1019, Condition A. As a result of this finding, samples from previously delivered wafer

SPO-2015-PIN-0003
Product Information Notice is to inform the industry about the CAES SRAMs low power read architecture

SPO-2012-PCN-0010
SEE & Package drawing clarification and Pin Description correction

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