Clock Management
UT7R2XLR816 Clock Network Manager
- Clock banks
- 8
- Output frequency
- 750 kHz to 200 MHz
- Input reference frequency
- 2 MHz to 200 MHz
Specifications
| Part Number | UT7R2XLR816 |
|---|---|
| Flight Grade | QML-Q, QML-Q+ |
| LET (MeV·cm²/mg) | ≤109 |
| TID krad(Si) | 100 |
| # of Clocks | 16 |
| Frequency | 750kHz to 250MHz |
| Supply Voltage | +2.25V to +3.6V |
| Package | 168-lead CLGA 168-lead CCGA |
Technical specifications
| Specification | Value |
|---|---|
| Clock banks | 8 |
| Output frequency | 750 kHz to 200 MHz |
| Input reference frequency | 2 MHz to 200 MHz |
| Core supply | 3.3 V |
| Output-bank supplies | 2.25 V to 3.6 V |
| Input multiplication | Integer factors 1 through 32 |
Values are subject to the conditions and ordering options in the referenced product documentation.
Product overview
The UT7R2XLR816 clock network manager combines a PLL with eight configurable output banks. Each bank has an independent supply and can provide LVCMOS signaling; the device also supports LVDS output configurations. Programmable multiplication, division, and phase controls allow reference-clock distribution to be adapted to the system timing requirements. Inputs support LVCMOS/LVTTL, LVDS, or a parallel-resonant quartz crystal. A dedicated feedback module maintains PLL operation, while synchronous output-enable and bank power-down controls manage the distributed clocks. Output frequencies extend from 750 kHz to 200 MHz.
Documentation
Technical documents and resources
For product questions or additional technical information, contact Frontgrade https://www.frontgrade.com/contact-us-form.
Datasheet
Application Notes
IBIS Models
More about this product
Product features
- Eight independently supplied clock banks
- Configurable LVCMOS or LVDS signaling
- Programmable multiplication, division, and phase
- Dedicated feedback module
Clock-bank configuration
Each bank has an independent supply and can provide LVCMOS signaling; the device also supports LVDS output configurations. Programmable multiplication, division, and phase controls allow reference-clock distribution to be adapted to the system timing requirements. Inputs support LVCMOS/LVTTL, LVDS, or a parallel-resonant quartz crystal.
Applications
- Clock generation and distribution
Discuss your application
Contact Frontgrade to discuss UT7R2XLR816 Clock Network Manager and the requirements of your application.