UT24C407 Certus™-NX-RT
Part Number | Grade | LET (MeV-cm^2/mg) | TID krad(Si) | Logic Cells | Package |
---|---|---|---|---|---|
UT24C407 | Space PEM QD | ≤80 | 100 | 39000 | 256-Lead PBGA |

Datasheet
Product Brief
Application Notes
- Creating a-SoC Project
- Creating Radiant Project
- Debug with ModelSim
- IBIS Model
- ADC User Guide
- Scrubber(SEDC) User Guide
- PLL User Guide
- Configuration User Guide
- Internal Memory User Guide
- Configuration/Programming FAQ
- Multi-boot User Guide
- DSP User Guide
- Schematic ECAD (Orcad)
- High Speed I/O User Guide
- BSDL File, Certus-NX Versa Eval Board, Adiuvo Evaluation Board links
Certus™-NX-RT FPGAs are purpose-built for space missions with SnPb solder ball leads and are produced from single, traceable wafer lots that have passed radiation acceptance testing.

These small, power-efficient FPGAs have 39K logical cells that are supported with 2.5Mb of on-die memory, analog features and wideband interfaces making them ideally suited to efficient, scalable distributed processing architectures.
Key Features:
- 28 nm FD-SOI technology for SWaP and radiation performance
- 39K programmable logic cells
- 2.5 Mb (EBR and LRAM) embedded memory
- Max Image Size (with maximum LRAM and EBR) is 8.807 Mb
- Gen1/2 PCIe, SGMII (Gigabit Ethernet), LVDS, LVCMOS and more interfaces
- Dual 12-bit ADCs
- Expert radiation and FPGA technical support
- Comprehensive suite of development tools and fault-tolerant libraries
- Programmable Core
- Low-power mode
- High-performance mode
- High embedded memory count
- DSP blocks
- Hard Macro Blocks
- One lane PCIe (5 Gbps)
- CDR for SGMII (1.25 Gbps)
- ADC
- Fast Programmable I/O
- Diff I/O (1.5 Gbps)
- LVDS, subLVDS, SGMII
- DDR3 (1066 Mbps)
- Up to 192 total I/O
Physical:
- Plastic package, SnPb balling (x256)
- 14 mm x 14 mm, 0.8 mm pitch
Operational Environment:
- Temperature Range: -40°C to 125°C
- Total Ionizing Dose: <100 krad (Si)
- SEL Immune: ≤80 MeV-cm2/mg
Power:
- 100 mW (typical)
Voltage:
- Supply Voltage (Core): 1.0V
- Supply Voltage (Aux): 1.8V
- I/O Voltage Range: 1.0V - 3.3V
Primary I/O:
- LVDS
- Soft D-PHY
- SGMII
- PCIe
- GbE
Phase-Locked Loop (PLL):
- 3
SERDES:
- 4 Lanes
Supported Memory:
- DDR2/3L x8 or x16
- LPDDR2/3 x8 or x16
ADC:
- 2x 1 MSPS
- 12-bit SAR
Security:
- Bit stream encryption (AES-256) & authentication (ECDSA)
Datasheet
Product Brief
Application Notes
- Creating a-SoC Project
- Creating Radiant Project
- Debug with ModelSim
- IBIS Model
- ADC User Guide
- Scrubber(SEDC) User Guide
- PLL User Guide
- Configuration User Guide
- Internal Memory User Guide
- Configuration/Programming FAQ
- Multi-boot User Guide
- DSP User Guide
- Schematic ECAD (Orcad)
- High Speed I/O User Guide
- BSDL File, Certus-NX Versa Eval Board, Adiuvo Evaluation Board links