SRAM

UT8R1M39 40Mb SRAM Module

40 Mb asynchronous SRAM module with 1M × 39 organization, 20 ns read access and a 39-bit data path.
SEL characterization
≤110 MeV·cm²/mg
Type
SRAM
Part
UT8R1M39
Specifications

Specifications

Product specifications
Part Number UT8R1M39
Flight Grade QML-Q, QML-V
LET (MeV·cm²/mg) ≤110
TID krad(Si) 100
Access Time 20ns
Configuration 1M x 39
Density 40Mb
Supply Voltage +2.5V
Package 132-Lead FP

Technical specifications

Specification Value Notes
Density and organization 40 Mb; 1M × 39 Exact organization determines usable data width; the x39 family is marketed as 40/80/160 Mb.
Read/write access 20 ns read; 10 ns write Use this density-specific option; the family feature heading does not make all densities 20 ns.
I/O and core supplies I/O: 2.3–3.6 V; core: 1.7–2.0 V
Package 132-lead side-brazed dual-cavity ceramic quad flatpack
HiRel operating range −55°C to +105°C Prototype flow is 25°C only.
SMD radiation assurance 100 krad(Si) SMD R option. Generic HiRel and prototype flows do not test or guarantee radiation.
SEL characterization ≤110 MeV·cm²/mg

Values are subject to the conditions and ordering options in the referenced product documentation.

Product overview

The UT8R1M39 is a 40 Mb CMOS static RAM multichip module organized as 1M × 39. It combines two SRAM die in a 132-lead ceramic quad flatpack and provides 20 ns read access with 10 ns write access. Active-low chip enables, output enable and three-state drivers support memory expansion and bus control. Its 39-bit-wide organization supports systems using external error-detection and correction logic. A deselected power-down mode reduces consumption while preserving stored data. Core and I/O supplies are separate, and the selected SMD ordering configuration defines radiation assurance, temperature range and quality level.

More about this product

Product features

  • Asynchronous SRAM interface
  • Separate I/O and core supplies
  • Three-state bidirectional data bus
  • Deselected power-down mode
  • External EDAC support

Memory expansion and bus control

Active-low chip enables, output enable and three-state drivers control individual memory die. Only one die enable may be active at a time.

Applications

  • Microprocessor memory
  • Microcontroller memory
  • FPGA memory
Product support

Discuss your application

Contact Frontgrade to discuss UT8R1M39 40Mb SRAM Module and the requirements of your application.