LVDS
UT54LVDS218 Deserializer
- Type
- LVDS
- Part
- UT54LVDS218
- Capability
- Microelectronics
Specifications
| Part Number | UT54LVDS218 |
|---|---|
| Flight Grade | QML-Q, QML-V |
| LET (MeV·cm²/mg) | ≤100 |
| TID krad(Si) | 1000 |
| Supply Voltage | +3.3V |
| Throughput | 1.575 Gbps |
| Package | 48-lead FP |
Technical specifications
| Specification | Value | Notes |
|---|---|---|
| Parallel data width | 21 bits | Follow exact SMD ordering and channel timing conditions. |
| Shift-clock range | 15 MHz to 75 MHz | Follow exact SMD ordering and channel timing conditions. |
| Aggregate throughput | Up to 1.575 Gbps | Follow exact SMD ordering and channel timing conditions. |
| Package | 48-lead flatpack | Follow exact SMD ordering and channel timing conditions. |
| Radiation options | 300 krad(Si) and 1 Mrad(Si) | Follow exact SMD ordering and channel timing conditions. |
Values are subject to the conditions and ordering options in the referenced product documentation.
Product overview
The UT54LVDS218 deserializer converts three LVDS data streams into 21 bits of parallel CMOS/TTL data. The receiver recovers parallel data and provides an output clock with a 50% duty cycle. With a 75 MHz clock, each data channel carries 525 Mbps for an aggregate data throughput of 1.575 Gbps. The narrower differential interface reduces cable size and electromagnetic emissions relative to a wide parallel interface. The PLL requires no external components. Cold-spare buffers on all pins present a high impedance when the supply is tied to ground.
Documentation
Technical documents and resources
For product questions or additional technical information, contact Frontgrade https://www.frontgrade.com/contact-us-form.
Datasheet
Application Notes
IBIS Models
More about this product
Product features
- 21-bit parallel interface
- Three LVDS data channels
- PLL without external components
- Cold sparing on all pins
Parallel-to-serial data transport
The receiver recovers parallel data and provides an output clock with a 50% duty cycle. With a 75 MHz clock, each data channel carries 525 Mbps for an aggregate data throughput of 1.575 Gbps. The narrower differential interface reduces cable size and electromagnetic emissions relative to a wide parallel interface.
Applications
- High-speed parallel-interface serialization
Discuss your application
Contact Frontgrade to discuss UT54LVDS218 Deserializer and the requirements of your application.