SRAM
UT9Q512K32 16Mb QCOTS SRAM
- Density and organization
- 16 Mb; 512K × 32
- Maximum address access
- 25 ns at 5 V
- Interface
- Asynchronous; TTL-compatible I/O
Specifications
| Part Number | UT9Q512K32 |
|---|---|
| Flight Grade | QML-Q, QML-V |
| LET (MeV·cm²/mg) | ≤100 |
| TID krad(Si) | 100 |
| Access Time | 25ns |
| Configuration | 512K x 32 |
| Density | 16Mb |
| Supply Voltage | +5.0V |
| Package | 68-Lead FP |
Technical specifications
| Specification | Value | Notes |
|---|---|---|
| Density and organization | 16 Mb; 512K × 32 | |
| Maximum address access | 25 ns at 5 V | |
| Interface | Asynchronous; TTL-compatible I/O | |
| Package | 68-lead dual-cavity ceramic quad flatpack | |
| SMD radiation-assurance options | 50 or 100 krad(Si) | Total-dose assurance must be specified in the order; generic screening flow does not guarantee radiation. |
| Extended-industrial temperature | −40°C to +105°C | Prototype flow is 25°C only. |
Values are subject to the conditions and ordering options in the referenced product documentation.
Product overview
The UT9Q512K32E is a 16 Mb radiation-tolerant CMOS static RAM with 25 ns maximum address access at a 5 V supply. It contains four 512K × 8 memories with a common output enable; separate die controls support 8-, 16-, 24- or 32-bit accesses. TTL-compatible input and output levels and a three-state bidirectional bus support connection to the host memory interface. The device uses a 68-lead dual-cavity ceramic quad flatpack, with quality and radiation-assurance options defined by its SMD ordering code. Select the appropriate voltage, package and temperature configuration for the design, and use the radiation-assured ordering option when the application requires guaranteed total-dose performance.
Documentation
Technical documents and resources
For product questions or additional technical information, contact Frontgrade https://www.frontgrade.com/contact-us-form.
Datasheet
App Note
More about this product
Product features
- Asynchronous memory interface
- TTL-compatible input and output levels
- Three-state bidirectional data bus
- Flexible 8-, 16-, 24- or 32-bit accesses
Control the memory bus
Active-low chip enable, write enable and output enable control data access. Three-state output drivers isolate the device when deselected or writing.
Flexible access width
The four 8-bit memory die can be grouped through their chip-enable and write-enable controls for 8-, 16-, 24- or 32-bit accesses.
Discuss your application
Contact Frontgrade to discuss UT9Q512K32 16Mb QCOTS SRAM and the requirements of your application.