LVDS
UT54LVDS032LVT Quad CMOS Differential Line Receiver with Integrated 100 Ohm Termination Resistors
- Nominal supply
- 3.3 V
- Package
- 16-lead flatpack
- Integrated termination
- 100 Ω nominal
Specifications
| Part Number | UT54LVDS032LVT |
|---|---|
| Flight Grade | QML-Q, QML-V |
| LET (MeV-cm^2/mg) | ≤100 |
| TID krad(Si) | 1000 |
| Supply Voltage | +3.3V |
| Throughput | 400 Mbps |
| Package | 16-Lead FP |
Technical specifications
| Specification | Value | Notes |
|---|---|---|
| Interface function | quad LVDS line receiver with integrated termination | |
| Data rate | >400 Mbps | Switching rate as documented; follow datasheet loading and termination conditions. |
| Nominal supply | 3.3 V | |
| Package | 16-lead flatpack | |
| Integrated termination | 100 Ω nominal | |
| Documented radiation options | 300 krad(Si) and 1 Mrad(Si) | Options depend on exact SMD/RHA ordering code; not one rating for all variants. |
Values are subject to the conditions and ordering options in the referenced product documentation.
Product overview
The UT54LVDS032LVT is a quad LVDS line receiver with integrated termination that converts differential input signals to digital output levels. An integrated nominal 100 Ω termination resistor reduces external component count and board space. The receiver supports three-state outputs, fail-safe input behavior, and cold sparing on all pins. It uses low-voltage differential signaling to support high data rates with low power dissipation and reduced signal swing. The documented package is a 16-lead flatpack. Select the exact ordering option for the required screening level and radiation assurance.
Documentation
Technical documents and resources
For product questions or additional technical information, contact Frontgrade https://www.frontgrade.com/contact-us-form.
Datasheet
Application Notes
IBIS Models
More about this product
Product features
- Cold-spare buffers on all pins
- Output-enable control with high-impedance state
- Fail-safe receiver input behavior
- Integrated nominal 100 Ω termination
Differential signal interface
An integrated nominal 100 Ω termination resistor reduces external component count and board space. The receiver supports three-state outputs, fail-safe input behavior, and cold sparing on all pins.
Applications
- High-speed point-to-point interconnects
Discuss your application
Contact Frontgrade to discuss UT54LVDS032LVT Quad CMOS Differential Line Receiver with Integrated 100 Ohm Termination Resistors and the requirements of your application.