Logic Devices

UT54ACTS164E Registers 8-Bit Shift

UT54ACTS164E provides eight stages of shift-register storage with AND-gated serial inputs and asynchronous clear.
Logic function
8-bit shift register
Type
Logic Devices
Part
UT54ACTS164E
Specifications

Specifications

Product specifications
Part Number UT54ACTS164E
Flight Grade QML-Q, QML-V
LET (MeV·cm²/mg) ≤120
TID krad(Si) 1000
Input Buffer TTL
Supply Voltage =+3.3V+5V
Package 14-Lead Flat Pack

Technical specifications

Specification Value Notes
Logic function 8-bit shift register
Recommended supply voltage 3.0 to 5.5 V Recommended operating conditions; use the exact ACS or ACTS electrical table for input thresholds.
Operating case temperature -55°C to +125°C Recommended operating conditions; prototype screening may be room-temperature only.
Package options 14-lead flatpack Package availability depends on orderable variant.
Screening process options QML Q or QML V Select the applicable ordering option; prototype flow does not imply QML screening.
Total-dose capability Up to 1 Mrad(Si) Radiation-assured ordering option only; specify applicable SMD RHA level. Prototype/commercial flows do not imply radiation assurance.

Values are subject to the conditions and ordering options in the referenced product documentation.

Product overview

UT54ACTS164E provides eight stages of shift-register storage with AND-gated serial inputs and asynchronous clear. A low level at either serial input inhibits new data entry and resets the first stage at the next clock pulse. Shifting occurs on the low-to-high clock transition. Its recommended supply range is 3.0 to 5.5 V. The device is characterized over a case-temperature range of -55°C to +125°C. QML Q and QML V process options are documented; select the orderable device and screening level for the required application.

More about this product

Product features

  • AND-gated serial inputs and direct clear
  • QML Q and QML V process options

Logic operation

UT54ACTS164E provides eight stages of shift-register storage with AND-gated serial inputs and asynchronous clear. A low level at either serial input inhibits new data entry and resets the first stage at the next clock pulse. Shifting occurs on the low-to-high clock transition.

Applications

  • Serial data shifting
Product support

Discuss your application

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