SpaceWire
UT200SpWPHY01 Physical Layer Transceiver
- Type
- SpaceWire
- Part
- UT200SPWPHY01
- Capability
- Microelectronics
Specifications
| Part Number | UT200SpWPHY01 |
|---|---|
| Flight Grade | QML-Q, QML-V |
| LET (MeV·cm²/mg) | >109 |
| TID krad(Si) | 100 |
| Data Rate | 200 Mbps |
| Ports | 18 |
| Supply Voltage | +3.3V |
| Package | 28-lead FP |
Technical specifications
| Specification | Value | Notes |
|---|---|---|
| SerDes width | 2 bits | Radiation-assured ordering option where applicable. |
| Maximum data rate | 200 Mbps | Radiation-assured ordering option where applicable. |
| Supply | 3.3 V | Radiation-assured ordering option where applicable. |
| Package | 28-pin flatpack | Radiation-assured ordering option where applicable. |
| Total-dose capability | 100 krad(Si) | Radiation-assured ordering option where applicable. |
Values are subject to the conditions and ordering options in the referenced product documentation.
Product overview
The UT200SpWPHY01 is a SpaceWire physical-layer transceiver with two-bit serializer/deserializer functionality. Its receiver recovers data on both clock edges and presents bit pairs to the digital interface. The transmitter accepts data and strobe bit pairs, then serializes them onto the LVDS bus. This arrangement lets an interfacing FPGA or ASIC operate at a reduced clock rate without imposing a stringent high-speed clock phase relationship. The PHY supports data rates up to 200 Mbps, operates from 3.3 V, and provides cold sparing on the LVDS pins.
Documentation
Technical documents and resources
For product questions or additional technical information, contact Frontgrade https://www.frontgrade.com/contact-us-form.
Datasheet
Application Notes
More about this product
Product features
- Two-bit serializer/deserializer function
- LVDS physical interface
- Data/strobe timing handling
- Cold sparing on LVDS pins
SpaceWire timing interface
Its receiver recovers data on both clock edges and presents bit pairs to the digital interface. The transmitter accepts data and strobe bit pairs, then serializes them onto the LVDS bus. This arrangement lets an interfacing FPGA or ASIC operate at a reduced clock rate without imposing a stringent high-speed clock phase relationship.
Applications
- SpaceWire physical-layer interfaces
- FPGA and ASIC SpaceWire connections
Discuss your application
Contact Frontgrade to discuss UT200SpWPHY01 Physical Layer Transceiver and the requirements of your application.